Today, in many Systems on a Chip (SoC's), one or more regulated voltages are used to power various subsystems within a SoC. Various types of voltage regulators have been developed to supply regulated voltages to different subsystems within the SoC. In general, a voltage regulator generates a regulated output voltage from an input voltage. In low power applications, voltage regulators are often used to generate a lower regulated output voltage than the input voltage. One common type of such voltage regulator is a low dropout regulator (LDO). LDOs can generally be classified into two types, namely, n-type output LDOs and p-type output LDOs.
FIG. 1 shows a conventional n-type output LDO 100. LDO 100 includes an error amplifier 110, a pass transistor 120, a feedback resistor 130, and a resistor 140. Error amplifier 110 has a positive input terminal, a negative input terminal, an output, and a voltage supply input terminal. The voltage supply input terminal is coupled to a voltage supply Vdd, which can be at about 1.2V in some examples. The positive input terminal is configured to receive a reference voltage Vref. The negative input terminal is coupled to one end of feedback resistor 130 and one end of resistor 140. The other end of resistor 140 is coupled to ground. The output of error amplifier 110 is coupled to a gate of pass transistor 120. Pass transistor 120 is an n-type metal oxide semiconductor transistor (NMOS). Thus, LDO 100 is also referred to as an NMOS-output LDO. The drain of pass transistor 120 is configured to receive an input voltage Vin, which can be about 0.85V in some examples. Note that Vdd is higher than Vin typically for the conventional n-type output LDO 100. A source of pass transistor 120 is configured to produce an output voltage Vout of LDO 100. The source is also coupled to the other end of feedback resistor 130 so that Vout is feedback to error amplifier 110 via the feedback resistor 130. In other words, error amplifier 110, pass transistor 120, and feedback resistor 130 form a feedback loop within LDO 100. The output voltage Vout is provided to a load, which is represented by a load capacitor 150 and a current source 160, which are coupled to each other in parallel to the ground.
One important parameter that is often used to evaluate LDO's is power supply ripple rejection ratio (PSRR). It is a measure of the output ripple compared to the input ripple over a wide frequency range (e.g., 10 Hz to 10 MHz) and is expressed in decibels (dB). One common way to calculate PSRR for an LDO is:PSRR=20 log(Av/Avo),where Av is the open-loop gain of the LDO feedback loop and Avo is the gain from Vin to Vout with the LDO feedback loop open. Thus, PSRR measures how well the LDO rejects ripple coming from the input power supply at different frequencies.
Although the conventional n-type output LDO 100 can provide good PSRR and faster transient response, LDO 100 requires an additional higher voltage supply, namely, Vdd, to bias error amplifier 110. The other type of conventional LDO, p-type output LDO, does not require an additional higher voltage supply, and one example of such a LDO is discussed below.
FIG. 2 shows a conventional p-type output LDO 200. LDO 200 includes an error amplifier 210, a pass transistor 220, a feedback resistor 230, and a resistor 240. Error amplifier 210 has a positive input terminal, a negative input terminal, an output, and a voltage supply input terminal. Error amplifier 210 has a positive input terminal, a negative input terminal, an output, and a voltage supply input terminal. The voltage supply input terminal is coupled to an input voltage Vin. The negative input terminal is coupled to one end of feedback resistor 230 and one end of resistor 240. The other end of resistor 240 is coupled to ground. The output of error amplifier 210 is coupled to a gate of pass transistor 220. Pass transistor 220 is a p-type metal oxide semiconductor transistor (PMOS). The source of pass transistor 220 is configured to receive the input voltage Vin. A drain of pass transistor 220 is configured to produce an output voltage Vout of LDO 200. The drain is also coupled to the other end of feedback resistor 240. The output voltage Vout is provided to a load, which is represented by a load capacitor 250 and a current source 260, which are coupled to each other in parallel to the ground. The p-type output LDO 200 uses Vin to bias error amplifier 210, and hence, LDO 200 does not require any voltage supply in addition to Vin. However, LDO 200 suffers from poor PSRR at mid-range frequencies, and hence, typically requires a larger load capacitor 250 to reduce power supply rejection (PSR). The larger load capacitor 250 increases the size of LDO 200.
Accordingly, there is a need in the art to design a LDO that does not require any voltage supply in addition to the input voltage Vin, while providing better PSRR in all ranges of frequency.